ICX252 データシートの表示（PDF） - Sony Semiconductor

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ICX252

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Sony Semiconductor 

CXD3406GA

Serial interface clock internal loading characteristics (2)

VD

HD

Enlarged view

Example: During frame mode

VD

0.2VDDd

HD

SEN1

ts1

0.8VDDd

th1

0.2VDDd

∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.

Symbol

ts1

th1

(Within the recommended operating conditions)

Definition

SEN1 setup time, activated by the falling edge of VD

SEN1 hold time, activated by the falling edge of VD

Min. Typ. Max. Unit

0

ns

200

ns

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD3406GA at the timing shown in "Serial interface clock

internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is

loaded to the CXD3406GA and controlled at the rising edge of SEN1. See "Description of Operation".

SEN1

Output signal

0.8VDDd

tpdPULSE

(Within the recommended operating conditions)

Symbol

Definition

tpdPULSE Output signal delay, activated by the rising edge of SEN1

Min. Typ. Max. Unit

5

100 ns

– 12 –

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