78Q2120C データシートの表示（PDF） - TDK Corporation

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78Q2120C

10/100BASE-TX Transceiver

TDK Corporation 

78Q2120C

10/100BASE-TX Transceiver

transitions synchronously with respect to RX_CLK

and is asserted when the 78Q2120C is presenting

valid data on RXD[3:0]. RX_ER is asserted when a

code group violation has been detected in the

current receive packet and is also synchronous to

RX_CLK.

Station Management Interface

The station management interface consists of

circuitry which implements the serial protocol as

described in Clause 22.2.4.5 of IEEE-802.3. A 16-

bit shift register receives serial data applied to the

MDIO pin at the rising-edge of the MDC clock signal.

Once the preamble is received, the station

management control logic looks for the start-of-

frame sequence and a read or write op-code,

followed by the PHYAD and REGAD fields. For a

read operation, the MDIO port becomes enabled as

an output and the register data is loaded into a shift

register for transmission. The 78Q2120C can work

with a one bit preamble rather than the 32 bits

proscribed by IEEE-802.3. This allows for faster

programming of the registers. If a register does not

exist at an address indicated by the REGAD field or

if the PHYAD field does not match the 78Q2120C

PHYAD indicated by the PHYAD pins, a read of the

MDIO port will return all ones. For a write operation,

the data is shifted in and loaded into the appropriate

register after the sixteenth data bit has been

received.

When the PHYAD field is all zeros, the Station

Management Entity (STA) is requesting a broadcast

data transaction. All PHYs sharing the same

Management Interface must respond to this

broadcast request. The 78Q2120C will respond to

the broadcast data transaction.

ADDITIONAL FEATURES

LED Indicators

There are seven LED pins that can be used to

indicate various states of operation of the

78Q2120C. There is an LED pin that indicates the

link is up (LEDL), others that indicates the

78Q2120C is either transmitting (LEDTX) or

receiving (LEDRX), one that signals a collision event

(LEDCOL), two more that reflect the data rate

(LEDBTX and LEDBT), and one that reflects full

duplex mode of operation (LEDFDX).

Interrupt Pin

The 78Q2120C has an Interrupt pin (INTR) that is

asserted whenever any of the eight interrupt bits of

MR17.7:0 are set. These interrupt bits can be

disabled via MR17.15:8 Interrupt Enable bits. The

Interrupt Level bit, MR16.14, controls the active level

of the INTR pin. When the INTR pin is not asserted,

the pin is held in a high impedance state.

© 2003 TDK Semiconductor Corporation, Proprietary and Confidential

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Rev_1.1

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