MC44864 データシートの表示（PDF） - Motorola => Freescale
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MC44864 Datasheet PDF : 12 Pages
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MC44864
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third data byte
is ignored. If five or more data bytes are received, the fifth
and following data bytes are ignored and the last
acknowledge pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit F. If
the function bit F= 0, frequency information is acknowledged
and if F = 1, control/band information is acknowledged.
If the address is correct (signal AD1) the information is
loaded into latches.
A function bit in the first and third data byte is used to pass
this data either into the latches of the programmable divider
(signal DTF) or into the latches for band and control information
(signal DTB). The data transfer to the latches (signals DTF and
DTB) is initiated after the 2nd and 4th data bytes.
A second string of latches is used for the data transfer into
the programmable divider to inhibit the transfer during the
preset operation (signal TDI, signal AVA is an internal
“address valid” command).
The switching levels of clock and data (Pins 18 and 19) are
0.5 x VCC1.
The control and band information bits have the following
functions.
Bits R0, R1: Controls Reference Divider Division Ratio
R0
R1
Division Ratio
0
0
1
0
0
1
1
1
2048
1024
512
256
Bits R2, R3: Switches Internal Signals to the Buffer
Outputs
R2
R3
Pin 16
Pin 17
0
0
–
–
0
1
62.5 kHz
–
1
0
Fref
FBY2
1
1
–
–
Bit B5 has to be “one” when Pin 16 is used to output 62.5
kHz. Bits B5 and B7 have to be “one” to output Fref and FBY2.
FBY2 is the programmable divider output frequency divided
by two.
Bits R2, R6, T: Controls the Phase Comparator Output
Stage
R2
R6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
T
Output State
0 Normal Operation
1
“Off” (High Impedance)
0
High
1
Low
0
Normal Operation
1
“Off”
0
1
Normal Operation
“Off”
The Band Buffers
The band buffers are open collector transistors and are
active “low” at Bn = 1. They are designed for 15 mA with
typical on–voltage of 1.8 V. These buffers are designed to
withstand relative high output voltage in the off–state (15 V).
B5 and B7 buffers (Pins 16 and 17) may also be used to
output internal IC signals (reference frequency and
programmable divider output frequency divided by 2) for test
purposes.
Buffer B5 may also be used to output a 62.5 kHz frequency
from an intermediate stage of the reference divider. The bits
B5 and B7 have to be “one” if the buffers are used for these
additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
Minimum Ratio 256
where N0 … N14 are the different bits for frequency
information.
The counter reloads correctly as long as its output
frequency does not exceed 1.0 MHz.
Division ratios of < 256 are not allowed. At power–up the
counter bit N8 is preset to “1”. All other bits are undetermined.
In this way, the counter always starts with a division ratio of
256 or higher.
The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the bus.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The prescaler has a preamplifier and may be bypassed
(Bit P). The signal then passes through preamplifier 2.
The table on the following page shows the frequency
ranges which may be synthesized with and without prescaler.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier for the tuning voltage is designed
for low noise, low input bias current and high power supply
rejection. The positive input is biased internally. The
operational amplifier needs 30 V supply (VCC2) as minimum
voltage for a guaranteed maximum tuning voltage of 28.5 V.
Figure 4 shows the usual filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 4 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
The Oscillator
The oscillator uses a 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The crystal is driven through a 1.6 kΩ resistor on chip.
The voltage at Pin 16 “crystal”, has low amplitude and low
harmonic distortion.
The negative resistance of the oscillator at Pin 1 (XTAL) is
about 3.0 kΩ.
MOTOROLA ANALOG IC DEVICE DATA
9
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