QL6250-E データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

4/( (FOLSVH( 'DWD 6KHHW 5HY $

CLK

D

tSU

tHL

Q

tCO

)LJXUH  /RJLF &HOO )OLS)ORS 7LPLQJV²6HFRQG :DYHIRUP

Quad net

H

&ORFN 6RXUFH

Logic Cells (Internal)

Clock Pad

)LJXUH  (FOLSVH( *OREDO &ORFN 6WUXFWXUH

7DEOH  (FOLSVH( &ORFN 'HOD\

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

*OREDO

'HGLFDWHG

Clock signal generated internally 1.51 ns (max)

Clock signal generated externally 2.06 ns (max)

1.73 ns (max)



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Preliminary ‹  4XLFN/RJLF &RUSRUDWLRQ

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