ST1284-02 データシートの表示（PDF） - STMicroelectronics

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ST1284-02

PARALLEL PORT SINGLE TERMINATION NETWORK WITH ±15kV ESD PROTECTION

STMicroelectronics 

ST1284-xxA8

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and

Rload>Rd, it gives these formulas:

Vinput = Rg.VBR + Rd.VPP

Rg

Voutput = Rt.VBR + Rd.Vinput

Rt

The results of the calculation done for VPP=8kV, Rg=330Ω (IEC61000-4-2 standard), VBR=7V (typ.)

and Rd = 1Ω (typ.) give:

Vinput = 31.2 V

Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the

low current involved after the resistance R.

The measurements done here after show very clearly (Fig. A5) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Vout stage

- Voutput clamping voltage very close to VBR (positive strike) and -VF (negative strike)

Fig. A4: Measurement conditions.

ESD

SURGE

Vinput

ST1284

Voutput

Fig. A5: Remaining voltage at the input and output of the device during a ±16kV ESD surge

(IEC61000-4-2).

5/6

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