SST25VF020B データシートの表示（PDF） - Microchip Technology

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SST25VF020B

2 Mbit SPI Serial Flash

Microchip Technology 

A Microchip Technology Company

2 Mbit SPI Serial Flash

SST25VF020B

Data Sheet

Read-Status-Register (RDSR1)

The Read-Status-Register 1 (RDSR1) instruction allows reading of the status register 1. CE# must be

driven low before the RDSR instruction is entered and remain low until the status data is read. Read-

Status-Register 1 is continuous with ongoing clock cycles until it is terminated by a low to high transi-

tion of the CE#. See Figure 17 for the RDSR instruction sequence.

CE#

MODE 3 0

1

2

3

4

5

6

SCK MODE 0

SI

35

MSB

HIGH IMPEDANCE

SO

7

8

9 10 11 12 13 14

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB

Status

Register Out

1417 RDSR1seq.0

Figure 17:Read-Status-Register 1 (RDSR1) Sequence

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to 1 allow-

ing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/

Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Reg-

ister (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared

upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruc-

tion is executed.

CE#

MODE 3

SCK MODE 0

0 1 2345 6 7

SI

06

MSB

SO

HIGH IMPEDANCE

1417 WREN.0

©2011 Silicon Storage Technology, Inc.

20

S71417-03-000

02/11

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