AS1155 データシートの表示（PDF） - austriamicrosystems AG

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AS1155

Single/Dual LVDS Receivers

austriamicrosystems AG 

AS1153/55

Data Sheet - Package Drawings and Markings

10 Package Drawings and Markings

The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package.

Figure 22. 8-pin SOIC Package Diagram

Table 6. 8-pin SOIC Package Dimensions

SOIC - 8LD

Symbol

MILLIMETERS

MIN

MAX

Symbol

A1

0.10

0.25

h

B

0.36

0.48

L

D

4.80

4.98

A

E

3.81

3.99

e

1.27 BSC

ZD

H

5.80

6.20

A2

MILLIMETERS

MIN

MAX

0.25

0.50

0.41

1.27

1.52

1.72

0º

8º

0.53 REF

1.37

1.57

Note:

1. Lead coplanarity should be 0 to 0.10MM max.

2. Package surface finishing:

Top: Matte (Charmilles #18~30)

All Sides: Matte (Charmilles #18~30)

Bottom: Smooth or Matte (Charmilles #18~30)

3. All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D)

4. Details of PIN #1 identifier are optional, but must be located within the zone indicated.

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