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NJU3430 データシートの表示(PDF) - Japan Radio Corporation

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NJU3430 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
NJU3430
n Interface with MPU
The instruction and RAM data are input through the serial port. The data form is 8-bit per word, and data transfer
is performed by synchronizing clock. The shift clock is input from external, and the data is loaded at the rising
edge of the shift clock.
One time transfer is executed by 8-bit unit. The transfer period is from falling edge to rising of the CS signal from
external. Therefore, when the rising edge of the CS signal is input, the operation is started. When more than 8-bit
data is input, the last 8-bit data is valid.
The input data is judged as instruction or RAM data by the RS signal at the rising edge of the CS signal (RS=”H”
: RAM data, RS=”L” : Instruction). When the input data is RAM data, the RAM address is increased one by one
automatically after data writing.
CS
CLK
RS
SI
B7 B6 B5 B4 B3 B2 B1 B0
MSB
[For example]
DD RAM writing
LSB
1Byte
(Instruct ion)
Select the Address
B7 B6 B5 B4 B3 B2 B1 B0
MSB
LSB
2Byte
(Data)
Character Code Data
B7 B6 B5 B4 B3 B2 B1 B0
MSB
LSB
3Byte
(Data)
Character Code Data
of the Next Address
n ABSOLUTE MAXIMUM RATINGS
P A R A M E T E R SYMBOL
Supply Voltage (1)
V DD
Supply Voltage (2)
V FDP
Input Voltage
V IN
Power Dissipation
Storage Temperature
Operating
Temperature
PD
T stg
Topr
IO 1
IO 2
Output Current
IO 3
Total Output Current
IO 4
Σ IOH
Σ IO L
RATINGS
-0.3 to 6.5
-40 to V DD +0.3
-0.3 to V DD +0.3
800
-55 to 125
-40 to 85
-40
-20
-10
-4.0
-100
100
UNIT
V
V
V
mW
°C
°C
mA
mA
mA
mA
mA
mA
CONDITIONS
Ta 2 5 ° C Q F P - 6 4
T1 - T16
MK1 - MK2
S 1 - S 35
P1(LED drive is available)
All Terminals at "H" level
All Terminals at "L" level
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the
LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electric characteristics conditions will cause malfunction and poor reliability.
Note 2) Decoupling capacitor should be connected between VDD and VSS, VFDP and VSS due to the stabilized
operation for the LSI.
Note 3) All voltage values are specified as VSS = 0V.
The relation : VDD > VSS, VDD> VSS VFDP, VSS=0V must be maintained.

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