AT32UC3L0128-ZAUR データシートの表示（PDF） - Atmel Corporation

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AT32UC3L0128-ZAUR

32-bit Atmel AVR Microcontroller

Atmel Corporation 

Figure 4-2. The AVR32UC Pipeline

IF

ID

Prefetch unit Decode unit

Regfile

Read

AT32UC3L0128/256

MUL

Multiply unit

ALU

LS

Regfile

write

ALU unit

Load-store

unit

4.3.2

AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-

geted at cost-sensitive, lower-end applications like smaller microcontrollers. This

microarchitecture does not provide dedicated hardware registers for shadowing of register file

registers in interrupt contexts. Additionally, it does not provide hardware registers for the return

address registers and return status registers. Instead, all this information is stored on the system

stack. This saves chip area at the expense of slower interrupt handling.

4.3.2.1

Interrupt Handling

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These

registers are pushed regardless of the priority level of the pending interrupt. The return address

and status register are also automatically pushed to stack. The interrupt handler can therefore

use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are

restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.

Executing the rete or rets instruction at the completion of an exception or system call will pop

this status register and continue execution at the popped return address.

4.3.2.2

Java Support

AVR32UC does not provide Java hardware acceleration.

4.3.2.3

4.3.2.4

Memory Protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is

attempted to an illegal memory address, the access is aborted and an exception is taken. The

MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

Unaligned Reference Handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is

able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an

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32145C–06/2013

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