MBM29LV800BA-120PFTR データシートの表示（PDF） - Fujitsu

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MBM29LV800BA-120PFTR

CMOS 8M (1M × 8/512K × 16) BIT

Fujitsu 

MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12

s AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

JEDEC Standard

Description

Test Setup

tAVAV

tAVQV

tRC Read Cycle Time

tACC Address to Output Delay

— Min.

CE = VIL

OE = VIL

Max.

tELQV

tCE Chip Enable to Output Delay

OE = VIL Max.

tGLQV

tOE Output Enable to Output Delay

— Max.

tEHQZ

tDF Chip Enable to Output High-Z

— Max.

tGHQZ

tDF Output Enable to Output High-Z

— Max.

tAXQX

tOH

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

—

Min.

—

tREADY RESET Pin Low to Read Mode

— Max.

—

tELFL

tELFH

CE or BYTE Switching Low or High

—

Max.

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29LV800TA/BA-70)

1 TTL gate and 100 pF (MBM29LV800TA/BA-90/-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output:1.5 V

-70

(Note)

70

70

70

30

25

25

0

20

5

-90

(Note)

-12

(Note)

Unit

90

120 ns

90

120 ns

90

120 ns

35

50 ns

30

30 ns

30

30 ns

0

0

ns

20

20 µs

5

5

ns

Device

Under

Test

CL

3.3 V

IN3064

or Equivalent

2.7 kΩ

6.2 kΩ

Diodes = IN3064

or Equivalent

Notes: CL = 30 pF including jig capacitance (MBM29LV800TA/BA-70)

CL = 100 pF including jig capacitance (MBM29LV800TA/BA-90/-12)

Figure 4 Test Conditions

31

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