ST7528 データシートの表示（PDF） - Sitronix Technology Co., Ltd.
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ST7528 Datasheet PDF : 97 Pages
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ST7528
Name
Microprocessor Interface Pin Description (Continued)
I/O Description
E_RD I
Read / Write execution control pin
PS1 MPU Type
E_RD Description
H
6800-series
E
Read / Write control input pin
When RW = “H”: E is “H”, DB0 to DB7 are in an
output status.
When RW = “L”: The data on DB0 to DB7 are
latched at the falling edge of the E signal.
L
8080-series
/RD
Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
DB0
I/O 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus.
to
When chip select is not active (CSB=H), DB0 to DB7 may be high impedance.
DB7
When the 3-Line/4-Line serial interface selected (PS[2:0] = "000" or “010”);
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, D0 to D7 is high impedance.
When the IIC serial interface selected (PS[2:0] = "100");
D7: serial clock input (SCL)
D6 , D5 , D4: serial input data (SDA_IN)
D3, D2: (SDA_OUT) serial data acknowledge for the IIC interface. By connecting SDA_OUT to
SDA_IN externally, the SDA line becomes fully IIC interface compatible. Having the acknowledge
output separated from the serial data line is advantageous in chip on glass (COG) applications. In
COG application where the track resistance from the SDA_OUT pad to the system SDA line can be
significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It
is possible during the acknowledge cycle the ST7528 will not be able to create a valid logic 0 level.
By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that
ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to
guarantee a valid low level.
D6, D5, ….D2 must be connected together (SDA)
D1, D0: Is slave address (SA) bit1, 0, must connect to Vdd or Vss.
When chip select is not active, D0 to D7 is high impedance.
Ver2.3
19/97
2007/1/3
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