MPC8250AZQIHBC データシートの表示（PDF） - Freescale Semiconductor
部品番号
コンポーネント説明
メーカー
MPC8250AZQIHBC Datasheet PDF : 62 Pages
| |||
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3 Clock Configuration Modes
The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set
according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12.
Table 12. MPC8250 Clocking Modes
Pins
PCI_MODE PCI_CFG[0] PCI_MODCK 1
Clocking Mode
PCI Clock
Frequency Range
(MHZ)
Reference
1
—
—
Local bus
0
0
0
0
0
1
PCI host
0
1
0
0
1
1
PCI agent
1 Determines PCI clock frequency range. Refer to Section 3.2, “PCI Mode.”
—
50–66
25–50
50–66
25–50
Table 13 and Table 14
Table 15 and Table 16
Table 17 and Table 18
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to
the selected MPC8250 clock operation mode as described in the following sections.
NOTE
Clock configurations change only after POR is asserted.
3.1 Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are
available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
MODCK[1–3]
Input Clock
Frequency
CPM Multiplication CPM
Factor
Frequency
000
33 MHz
3
100 MHz
001
33 MHz
3
100 MHz
010
33 MHz
4
133 MHz
011
33 MHz
4
133 MHz
Core Multiplication
Factor
4
5
4
5
Core
Frequency
133 MHz
166 MHz
133 MHz
166 MHz
MPC8250 Hardware Specifications, Rev. 2
20
Freescale Semiconductor
Share Link: 