FM24CL64B(2014) データシートの表示（PDF） - Cypress Semiconductor

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FM24CL64B
(Rev.:2014)

64-Kbit (8K × 8) Serial (I2C) F-RAM

Cypress Semiconductor 

FM24CL64B

AC Switching Characteristics

Over the Operating Range

Parameter[5]

Alt.

Parameter

Description

fSCL[6]

SCL clock frequency

tSU; STA

Start condition setup for repeated Start

tHD;STA

Start condition hold time

tLOW

Clock LOW period

tHIGH

Clock HIGH period

tSU;DAT

tSU;DATA Data in setup

tHD;DAT

tHD;DATA Data in hold

tDH

Data output hold (from SCL @ VIL)

tR[7]

tr

Input rise time

tF[7]

tf

Input fall time

tSU;STO

STOP condition setup

tAA

tVD;DATA SCL LOW to SDA Data Out Valid

tBUF

Bus free before new transmission

tSP

Noise suppression time constant on SCL, SDA

Min Max Min

– 0.1 –

4.7 – 0.6

4.0 – 0.6

4.7 – 1.3

4.0 – 0.6

250 – 100

0

–

0

0

–

0

– 1000 –

– 300 –

4.0 – 0.6

–

3

–

4.7 – 1.3

–

50

–

Max

0.4

–

–

–

–

–

–

–

300

300

–

0.9

–

50

Min

–

0.25

0.25

0.6

0.4

100

0

0

–

–

0.25

–

0.5

–

Max Unit

1.0 MHz

– s

– s

– s

– s

– ns

– ns

– ns

300 ns

100 ns

– s

0.55 s

– s

50 ns

Figure 14. Read Bus Timing Diagram

tR

` tF

tHIGH

tLOW

tSP

tSP

SCL

tSU:SDA

tBUF

SDA

1/fSCL

tHD:DAT

tSU:DAT

Start

Stop Start

tAA

tDH

Acknowledge

Figure 15. Write Bus Timing Diagram

SCL

SDA

tSU:STO

tHD:DAT

tHD:STA

tSU:DAT

tAA

Start

Stop Start

Acknowledge

Notes

5. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified

IOL and load capacitance shown in Figure 13.

6. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max).

7. These parameters are guaranteed by design and are not tested.

Document Number: 001-84458 Rev. *D

Page 12 of 19

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