FM24CL64B データシートの表示（PDF） - Cypress Semiconductor

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FM24CL64B

64-Kbit (8K × 8) Serial (I2C) F-RAM

Cypress Semiconductor 

FM24CL64B

Power Cycle Timing

Over the Operating Range

Parameter

tPU

tPD

tVR [9, 10]

tVF [9, 10]

Description

Power-up VDD(min) to first access (START condition)

Last access (STOP condition) to power-down (VDD(min))

VDD power-up ramp rate

VDD power-down ramp rate

Min

Max Unit

1

–

ms

0

–

µs

30

–

µs/V

30

–

µs/V

Figure 16. Power Cycle Timing

VDD

VDD(min)

tVR

tPU

VDD(min)

tVF

tPD

SDA

I2C START

I2C STOP

Note

9. Slope measured at any point on the VDD waveform.

10. Guaranteed by design.

Document Number: 001-84458 Rev. *I

Page 12 of 18

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