S25FL127S
CS#
SCK
Figure 3.7 Dual Output Command
IO0
IO1
Phase
Instruction
Address
6 Dummy
Data 1 Data 2
CS#
SCK
IO0
IO1
IO2
IO3
Phase
Figure 3.8 Quad Output Command without Latency
Instruction
Address Data 1 Data 2 Data 3 Data 4 Data 5
CS#
SCK
IO0
IO1
Phase
Instruction
Figure 3.9 Dual I/O Command
Address
Dummy
Data 1
Data 2
Figure 3.10 Quad I/O Command
CS#
SCK
IO0
IO1
IO2
IO3
Phase
Instruction
Address Mode Dummy D1 D2 D3 D4
Additional sequence diagrams, specific to each command, are provided in Section 9. Commands on page 65.
Document Number: 001-98282 Rev. *F
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