IS43TR16256A(2012) データシートの表示（PDF） - Integrated Silicon Solution

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IS43TR16256A
(Rev.:2012)

512Mx8, 256Mx16 4Gb DDR3 SDRAM

Integrated Silicon Solution 

IS43/46TR16256A, IS43/46TR16256AL,

IS43/46TR85120A, IS43/46TR85120AL

2.4.7.3 Write Leveling Mode Exit

The following sequence describes how the Write Leveling Mode should be exited:

1. After the last rising strobe edge, stop driving the strobe signals. Note: From now on, DQ pins are in undefined driving

mode, and will remain undefined, until tMOD after the respective MR command.

2. Drive ODT pin low (tIS must be satisfied) and continue registering low.

3. After the RTT is switched off, disable Write Level Mode via MRS command.

4. After tMOD is satisfied, any valid command may be registered. (MR commands may be issued after tMRD ).

2.4.8 Extended Temperature Usage

a. Auto Self-refresh supported

b. Extended Temperature Range supported

c. Double refresh required for operation in the Extended Temperature Range (applies only for devices supporting the

Extended Temperature Range)

Mode Register Description

Field Bits

Description

Auto Self-Refresh (ASR)

when enabled, DDR3 SDRAM automatically provides Self-Refresh power management functions for all

supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER

ASR

MR2 (A6) during subsequent Self-Refresh operation

0 = Manual SR Reference (SRT)

1 = ASR enable

Self-Refresh Temperature (SRT) Range

If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation

SRT

MR2 (A7) If ASR = 1, SRT bit must be set to 0b

0 = Normal operating temperature range

1 = Extended operating temperature range

2.4.8 1 Auto Self-Refresh mode - ASR Mode

DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit

A6 = 1b and MR2 bit A7 = 0b. The DRAM will manage Self-Refresh entry in either the Normal or Extended (optional)

Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM

operating temperature changes, lower at low temperatures and higher at high temperatures.

If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0b.

If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the

operating temperature range required during Self-Refresh operation.

Support of the ASR option does not automatically imply support of the Extended Temperature Range.

Integrated Silicon Solution, Inc. – www.issi.com –

27

Rev. 00A

11/14/2012

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