S25FL032P データシートの表示（PDF） - Cypress Semiconductor
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S25FL032P Datasheet PDF : 60 Pages
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S25FL032P
32-Mbit 3.0 V Flash Memory
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede
S25FL032P. These are the factory-recommended migration paths. Refer to the S25FL-L Family datasheets for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Common Flash Interface (CFI) compliant: allows host system
Single power supply operation
to identify and accommodate multiple flash devices
– Full voltage range: 2.7 V to 3.6 V read and write operations Process technology
Memory architecture
– Manufactured on 0.09 m MirrorBit® process technology
– Uniform 64-KB sectors
n – Top or bottom parameter block (two 64-KB sectors (top
ig or bottom) broken down into 16 4-KB sub-sectors each)
s – 256-byte page size
e – Backward compatible with the S25FL032A device
D Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
ew – Program operations are on a page by page basis
N – Accelerated programming mode via 9-V W#/ACC pin
r – Quad Page Programming
fo Erase
d – Bulk erase function
e – Sector erase (SE) command (D8h) for 64-KB sectors
d – Sub-sector erase (P4E) command (20h) for 4-KB sectors
n – Sub-sector erase (P8E) command (40h) for 8-KB sectors
e Cycling endurance
m – 100,000 cycles per sector typical
m Data retention
co – 20 years typical
e Device ID
R – JEDEC standard two-byte electronic signature
t – RES command one-byte electronic signature for backward
No compatibility
Package option
– Industry Standard Pinouts
– 8-pin SO package (208 mils)
– 16-pin SO package (300 mils)
– 8-contact USON package (5 6 mm)
– 8-contact WSON package (6 8 mm)
– 24-ball BGA 6 8 mm package, 5 5 pin configuration
– 24-ball BGA 6 8 mm package, 6 4 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40-MHz clock rate
– FAST_READ (Serial): 104-MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80-MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 A (typical)
– Deep Power-Down Mode 3 A (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits
One time programmable (OTP) area for permanent, secure
to protect specified memory areas
identification; can be programmed and locked at the factory
or by the customer
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00650 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 19, 2017
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