LHF16KA7 データシートの表示（PDF） - Sharp Electronics

部品番号

コンポーネント説明

メーカー

LHF16KA7

Flash Memory 16M (2MB × 8/1MB × 16)

Sharp Electronics 

SHARP

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LHF16KA7

18

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4.12 Set Block Lock-Bit Command

A flexible block locking and unlocking scheme is

enabled via block lock-bits. The block lock-bits gate

program and erase operations With WP#=V,,,

individual block lock-bits can be set using the Set

Block Lock-Bit command. See Table 13 for a

summary of hardware and software write protection

options.

Set block lock-bit is executed by a two-cycle

command sequence. The set block lock-bit setup

along with appropriate block or device address is

written followed by either the set block lock-bit

confirm (and an address within the block to be

locked). The WSM then controls the set block lock-bit

algorithm. After the sequence is written, the device

automatically outputs status register data when read

(see Figure 12). The CPU can detect the completion

of the set block lock-bit event by analyzing the STS

pin output or status register bit SR.7.

When the set block lock-bit operation is complete,

status register bit SR.4 should be checked. If an error

is detected, the status register should be cleared.

The CUI will remain in read status register mode until

a new command is issued.

This two-step sequence of set-up followed by

execution ensures that block lock-bits are not

accidentally set. An invalid Set Block Lock-Bit

command will result in status register bits SR.4 and

SR.5 being set -to “1”. Also, reliable operations occur

only when Vcc=Vcc1,2 and VPP=VPPH,,2,s. In the

absence of this high voltage, block lock-bit contents

are protected against alteration.

block lock-bits can be cleared using only

Block Lock-Bits command. See Table 13 for :

summary of hardware and software write protectior

options.

Clear block lock-bits operation is executed by a two

cycle command sequence. A clear block lock-bit:

setup is first written. After the command is written, tht

device automatically outputs status register datr

when read (see Figure 13). The CPU can detec

completion of the clear block lock-bits event b!

analyzing the STS Pin output or status register bi

SR.7.

When the operation is complete, status register bi

SR.5 should be checked. If a clear block lock-bit erro

is detected, the status register should be cleared

The CUI will remain in read status register mode unti

another command is issued.

This two-step sequence of set-up followed b)

execution ensures that block lock-bits are no

accidentally cleared. An invalid Clear Block Lock-Bits

command sequence will result in status register bits

SR.4 and SR.5 being set to “1”. Also, a reliable clear

block lock-bits operation can only occur wher

Vcc=VccI12 and VPP=VPPH1,2/3.If a clear block lock.

bits operation is attempted while V,+V,,,,, SR.3

and SR.5 will be set to “1”. In the absence of this high

voltage, the block lock-bits content are protectec

against alteration. A successful clear block lock-bits

operation requires WP#=V,,. If it is attempted with

WP#=V,,, SR.1 and SR.5 will be set to “1’ and the

operation will fail. Clear block lock-bits operations

with V,,<RP# produce spurious results and should

not be attempted.

4 successful set block ‘lock-bit operation requires

rNP#=V,,. If it is attempted with WP#=V,L, SR.l and

SR.4 will be set to “1’ and the operation will fail. Set

Yock lock-bit operations with WP#<V,, produce

jpurious results and should not be attempted.

1.13 Clear Block Lock-Bits Command

If a clear block lock-bits operation is aborted due to

V,, or Vco transitioning out of valid range or RP#

active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits

is- required to initialize block lock-bit contents to

known values.

411set block lock-bits are cleared in parallel via the

Zlear Block Lock-Bits command. With WP#=V,,,

Rev.1.9

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