DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

KSZ9031RNX データシートの表示(PDF) - Microchip Technology

部品番号
コンポーネント説明
メーカー
KSZ9031RNX
Microchip
Microchip Technology Microchip
KSZ9031RNX Datasheet PDF : 78 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
KSZ9031RNX
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect
configuration. In this case, external pull-up or pull-down resistors should be added on the PHY strap-in pins to ensure
the PHY is configured to the correct pin strap-in mode.
TABLE 2-2: STRAP-IN OPTIONS - KSZ9031RNX
Pin Number Pin Name
35
PHYAD2
15
PHYAD1
17
PHYAD0
Type
Note 2-2
I/O
I/O
I/O
27
MODE3
I/O
28
MODE2
I/O
31
MODE1
I/O
32
MODE0
I/O
33
CLK125_EN
I/O
41
LED_MODE
I/O
Note 2-2 I/O = Bi-directional.
Description
The PHY address, PHYAD[2:0], is sampled and latched at power-up/
reset and is configurable to any value from 0 to 7. Each PHY address
bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY Address Bits [4:3] are always set to ‘00’.
The MODE[3:0] strap-in pins are sampled and latched at power-up/
reset and are defined as follows:
MODE[3:0]
0000
0001
0010
Mode
Reserved - not used
Reserved - not used
Reserved - not used
0011
Reserved - not used
0100
NAND tree mode
0101
Reserved - not used
0110
0111
1000
1001
1010
1011
Reserved - not used
Chip power-down mode
Reserved - not used
Reserved - not used
Reserved - not used
Reserved - not used
1100
1101
RGMII mode - Advertise 1000BASE-T full-duplex
only
RGMII mode - Advertise 1000BASE-T full- and half-
duplex only
1110
RGMII mode - Advertise all capabilities (10/100/1000
speed half-/full-duplex), except 1000BASE-T half-
duplex
1111
RGMII mode - Advertise all capabilities (10/100/1000
speed half-/full-duplex)
CLK125_EN is sampled and latched at power-up/reset and is
defined as follows:
Pull-up (1) = Enable 125 MHz clock output
Pull-down (0) = Disable 125 MHz clock output
Pin 41 (CLK125_NDO) provides the 125 MHz reference clock output
option for use by the MAC.
LED_MODE is sampled and latched at power-up/reset and is
defined as follows:
Pull-up (1) = Single-LED mode
Pull-down (0) = Tri-color dual-LED mode
DS00002117C-page 12
2016 Microchip Technology Inc.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]