74ALVT16543DGG データシートの表示（PDF） - NXP Semiconductors.

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74ALVT16543DGG

2.5 V/3.3 V ALVT 16-bit registered transceiver (3-State)

NXP Semiconductors. 

Philips Semiconductors

2.5 V/3.3 V 16-bit registered transceiver (3-State)

Product data sheet

74ALVT16543

FEATURES

• 16-bit universal bus interface

• 5 V I/O Compatible

• 3-State buffers

• Output capability: +64 mA/–32 mA

• TTL input and output switching levels

• Input and output interface capability to systems at 5 V supply

• Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Live insertion/extraction permitted

• Power-up 3-State

• Power-up reset

• No bus current loading when output is tied to 5 V bus

• Latch-up protection exceeds 500mA per JEDEC Std 17

• ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

QUICK REFERENCE DATA

DESCRIPTION

The 74ALVT16543 is a high-performance BiCMOS product

designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility

up to 5 V. The device can be used as two 8-bit transceivers or one

16-bit transceiver.

The 74ALVT16543 contains two sets of eight D-type latches, with

separate control pins for each set. Using data flow from A to B as an

example, when the A-to-B Enable (nEAB) input and the A-to-B Latch

Enable (nLEAB) input are LOW, the A-to-B path is transparent.

A subsequent LOW-to-HIGH transition of the nLEAB signal puts the

A data into the latches where it is stored and the B outputs no longer

change with the A inputs. With nEAB and nOEAB both LOW, the

3-State B output buffers are active and display the data present at

the outputs of the A latches.

Control of data flow from B to A is similar, but using the nEBA,

nLEBA, and nOEBA inputs.

Active bus-hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.

SYMBOL

PARAMETER

CONDITIONS

Tamb = 25 °C; GND = 0 V

TYPICAL

2.5 V 3.3 V

UNIT

tPLH

tPHL

CIN

CI/O

ICCZ

Propagation delay

nAx to nBx or nBx to nAx

Input capacitance DIR, OE

I/O pin capacitance

Total supply current

CL = 50 pF

VI = 0 V or VCC

Outputs disabled; VI/O = 0 V or VCC

Outputs disabled

1.8

1.6

2.7

1.8

ns

3

3

pF

9

9

pF

40

70

µA

ORDERING INFORMATION

PACKAGES

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE

–40 °C to +85 °C

–40 °C to +85 °C

TYPE NUMBER

74ALVT16543DL

74ALVT16543DGG

DWG NUMBER

SOT371-1

SOT364-1

LOGIC SYMBOL (IEEE/IEC)

56

1EN3 (BA)

54

G1

55

1C5

1

2EN4 (AB)

3

G2

2

2C6

29

7EN9 (BA)

31

G7

30

7C11

28

8EN10 (AB)

26

G8

27

8C12

5

∇3

5D

52

15

∇9

11 D

42

6D

4∇

12 D

10 ∇

6

51

16

41

8

49

17

40

9

48

19

38

10

47

20

37

12

45

21

36

13

44

23

34

14

43

24

33

SW00151

2004 Sep 14

2

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