AD9432 データシートの表示（PDF） - Analog Devices

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AD9432

12-Bit, 80 MSPS/105 MSPS ADC

Analog Devices 

AD9432

DIGITAL OUTPUTS

The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL-/CMOS-

compatible for lower power consumption. The output data

format is twos complement (see Table 6).

Table 6. Twos Complement Output Coding (VREF = 2.5 V)

Code

AIN − AIN (V)

Digital Output

+2047

1.000

0111 1111 1111

…

…

…

0

0

0000 0000 0000

−1

−0.00049

1111 1111 1111

…

…

…

−2048

−1.000

1000 0000 0000

The out-of-range (OR) output is logic low for normal operation.

During any clock cycle when the ADC output data (Dx) reaches

positive or negative full scale (+2047 or −2048), the OR output

goes high. The OR output is internally generated each clock cycle.

It has the same pipeline latency and propagation delay as the ADC

output data and remains high until the output data reflects an

in-range condition. The ADC output bits (Dx) do not roll over

and, therefore, remain at positive or negative full scale (+2047

or −2048) while the OR output is high.

VOLTAGE REFERENCE

A stable and accurate 2.5 V voltage reference is built into the

AD9432 (VREFOUT). In normal operation, the internal refer-

ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF

decoupling capacitor at VREFIN.

The input range can be adjusted by varying the reference voltage

applied to the AD9432. No appreciable degradation in performance

occurs when the reference is adjusted ±5%. The full-scale range

of the ADC tracks reference voltage changes linearly.

TIMING

The AD9432 provides latched data outputs, with 10 pipeline

delays. Data outputs are included or available one propagation

delay (tPD) after the rising edge of the encode command (see

Figure 2). The length of the output data lines and the loads

placed on them should be minimized to reduce transients

within the AD9432; these transients can detract from the

dynamic performance of the converter.

The minimum guaranteed conversion rate of the AD9432 is

1 MSPS. At internal clock rates below 1 MSPS, dynamic perfor-

mance may degrade. Therefore, input clock rates below 1 MHz

should be avoided.

During initial power-up, or whenever the clock to the AD9432

is interrupted, the output data will not be accurate for 200 ns or

10 clock cycles, whichever is longer.

Rev. F | Page 14 of 16

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