AD607 データシートの表示（PDF） - Analog Devices
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AD607 Datasheet PDF : 24 Pages
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AD607
of current exactly balances the 4.5 µA discharge current. (It
makes no difference what the actual value of VG is at that point,
since the AGC filter is an integrator.)
Thus, at 20 mV/dB
VRIPPLE = IT = 4.5 µA × 93 ns = 0.42 mV
C
1 nF
This corresponds to 0.021 dB, and the ripple will modulate the
gain by that amount over each cycle. The effect of such modula-
tion on the signal is hard to quantify, but it roughly translates to
a 2% amplitude modulation. Also, the gain ripple depends on
the scale factor. For this example, at GREF = 1.23 V and a
16.4 mV/dB scale factor, the gain ripple increases to 0.025 dB.
AGC Charge Time
When the gain is too high, the IF amplifier will be overdriven to
produce a square wave output (roughly) of ± 560 mV. If per-
fectly square and time- and amplitude-symmetric, this would be
sliced at the 300 mV level to generate a current of 76 µA/2, or
38 µA. After subtracting the 4.5 µA, we should have about 33 µA.
In fact, the maximum ramp-up current is about 20 µA, because
the waveform is not a crisp square wave (and as the loop ap-
proaches equilibrium it is more nearly sinusoidal). Thus, the
ramp-up rate is 20/4.5 = 4.4 times faster than the discharge rate.
In our example, a 1.6 V change will require about 1.5 ms using
C = 1 nF.
Applications Hints
Do not place a resistor from Pin 12 to Ground: The resistor
converts the integrator—ideal for AGC—into a low-pass filter.
An integrator needs no input to sustain a given output; a low-
pass filter does. This “input” is an INCREASED AMPLITUDE
required at IFOP. The AGC loop thus does not level the output
at IFOP.
Reasons for Using a Larger AGC Capacitor
1. In applications where gain modulation may be troublesome,
raise the capacitor from 1 nF to 2.7 nF; the 80 dB slew time
(at 20 mV/dB) is now close to 1 ms.
2. As the IF is lowered, the capacitor must be increased accord-
ingly if gain ripple is to be avoided. Thus, to achieve the
same ripple at 455 kHz requires the 1 nF capacitor to be in-
creased to 0.022 µF.
3. In AM applications, the AGC loop must not track the modu-
lation envelope. The objective should be that the gain should
not vary by more than the amount required to introduce, say,
1% THD distortion at the lowest modulation frequency, say,
300 Hz. Note that in AM applications it is the modulation
bandwidth that determines the required AGC filter capaci-
tor, not the IF.
4. In some applications, even slower AGC may be desired than
that required to prevent modulation tracking.
AD607 EVALUATION BOARD
The AD607 evaluation board (Figures 46 and 47) consists of an
AD607, ground plane, I/O connectors, and a 10.7 MHz band-
pass filter. The RF and LO ports are terminated in 50 Ω to
provide a broadband match to external signal generators to al-
low a choice of RF and LO input frequencies. The IF filter is at
10.7 MHz and has 330 Ω input and output terminations; the
board is laid out to allow the user to substitute other filters for
other IFs.
FDIN
VPOS
GND
FDIN
PRUP
LO
RF
C15
0.1µF
JUMPER
C11
10nF
R8
51.1Ω
C12
0.1µF
C13 0
R9
0
C10
1nF
R7
51.1Ω
C9
C14 0
1nF
R6
51.1Ω
R5
332Ω
R3
332Ω
R10
4.99kΩ
R11
OPEN
FDIN
VPS1
COM1
FLTR
PRUP
IOUT
C16 1nF
LOIP
QOUT
AD607
RFLO
VPS2
RFHI
DMIP
JUMPER
R4
0
GREF
MXOP
VMID
IFOP
COM2
GAIN
IFHI
C7
1nF
IFLO
VPOS
AD607 EVALUATION BOARD
(AS RECEIVED)
C1
0.1µF
R1
C3 10nF
1kΩ
C2 0.1µF
R2
316Ω
C4
47pF
C5
1nF
C6
0.1µF
C8
0.1µF
I
Q
IF
RSSI
VPOS
C18
SHORT
R14
51.1Ω
C17
10nF
R15
50kΩ
R12
OPEN
R13
50kΩ
FDIN
C19
ANYTHING
FDIN
R19
RSOURCE
C20
SHORT
R17
OPEN
R18
OPEN
R16
OPEN
FDIN
VMID
MOD FOR LARGE MAGNITUDE
AC COUPLED INPUT
VMID
MOD FOR DC COUPLED INPUT
REV. 0
Figure 46. Evaluation Board
–19–
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