CXL1517M データシートの表示（PDF） - Sony Semiconductor
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CXL1517M Datasheet PDF : 7 Pages
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CXL1517M/1518M
Notes)
1) Linearity testing
For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a
sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C
channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then
input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum
output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output
amplitude as Sout min. The linearity of the respective channels is defined as:
Lin. = Sout max – Sout min × 200 [%]
Sout max + Sout min
2) Calculation of insertion gain difference
As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin,
the insertion gain difference between channels ∆G as:
( ) ∆G = | 1 – 10
Gmax – Gmin
20
| × 100 [%]
3) Calculation of linearity difference
Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as:
∆LBC = | LB – LC | [%]
4) Cross-talk calculation
CRTa
: The cross-talk value of A channel when B and C channels are input
OUTA-a : The output value of A channel when A channel is input
SW3-a, SW4-a, SW5, 6-b
OUTA-bc : The output value of A channel when B and C channels are input
(Cross-talk component)
SW3-a, SW4-b, SW5, 6-a
CRTa =
OUTA-bc
OUTA-a
× 100 [%]
Clock Waveform Timing
(52.5) ∗
87.5ns
10ns
10ns
(140) ∗
210ns
XDL1
90%
50%
10%
90%
50%
10%
17.5ns
(52.5) ∗
87.5ns
10ns
10ns
XDL2
90%
50%
10%
–5–
90%
50%
10%
∗ The value in brackets is for CXL1517M.
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