PCD5042 データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

PCD5042

DECT burst mode controller

Philips Electronics 

Philips Semiconductors

DECT burst mode controller

Objective specification

PCD5042

6.5.3 SEAMLESS HANDOVER

Seamless handover guarantees that when speech

information is switched from one slot to another, no speech

samples are lost, added or displaced. Seamless handover

is achieved in the RF interface by:

• Using a look-up table containing the correct start

addresses of the B-fields in the data memory

• The RF receive and transmit blocks move data to/from

the data memory block in 4-bit nibbles.

6.5.4 RF CONTROL SIGNALS

The timing of the control signals to the RF section is fixed,

but such that an RF delay between 1.5 and 7 µs can be

tolerated. Only the transmitter ramp signal and the

synthesizer enable are programmable within certain limits.

6.5.5 SYNTHESIZER PROGRAMMING

To program a synthesizer, a 3-wire serial interface is used.

The signals on this interface are:

• S_ENABLE (enable)

• S_CLK (clock)

• S_DATA (data).

To program various types of synthesizers, a 3-byte shift

register is present. Three data formats are supported:

8, 16 or 24 bit words can be selected. The transfer of data

from a frequency table in the common data memory to the

shift register is under control of the PCC.

6.5.6 RSSI MEASUREMENT (see Fig.8)

The RSSI measurement in the PCD5042 RF-interface

block is done in 3 parts: a peak/hold detector, a 6-bit A/D

converter, and an RSSI control unit, which controls the

peak/hold detector and the A/D converter. Once per slot

time, a sample is fetched by the PCC and saved in the

appropriate area of the common data memory.

If the radio receiver is active in a particular time slot, the

RSSI value will automatically be measured in that slot.

Adjustment to the RSSI_AN input level can be made with

VREF.

handbook, full pagewidth

VREF

RF-INTERFACE

RSSI_AN

RSSI value

filtered width

= 30 µs

(τ =10 to 40 µs)

PEAK

HOLD

RSSI_AN

6-BIT

A/D

internal

6

RSSI

bus

RSSI

CTRL

PROCESSING

(HW)

(SW in PCC)

RSSI_CTR

start_AD

write in memory

MBH711

1996 Oct 31

Fig.8 RSSI measurement path.

13

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