CXP86541 データシートの表示（PDF） - Sony Semiconductor

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CXP86541

CMOS 8-bit Single Chip Microcomputer

Sony Semiconductor 

CXP86541/86549/86561

(5) I2C bus timing

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

Symbol

Pins

Conditions Min.

Max. Unit

SCL clock frequency

fSLC

SCL

0

100 kHz

Bus-free time before starting transfer

tBUF

SDA, SCL

4.7

µs

Hold time for starting transfer

tHD; STA

SDA, SCL

4.0

µs

Clock Low level width

tLOW

SCL

4.7

µs

Clock High level width

tHIGH

SCL

4.0

µs

Setup time for repeated transfers

Data hold time

tSU; STA

tHD; DAT

SDA, SCL

SDA, SCL

4.7

µs

0∗1

µs

Data setup time

tSU; DAT

SDA, SCL

250

ns

SDA, SCL rise time

tR

SDA, SCL

1

µs

SDA, SCL fall time

tF

SDA, SCL

300 ns

Setup time for transfer completion

tSU; STO

SDA, SCL

4.7

µs

∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.

Fig. 8. I2C bus transfer timing

SDA

SCL

tBUF

tR

tHD; STA

P

S

tLOW

tF

tHD; DAT

tHIGH

tSU; DAT

tHD; STA

tSU; STA

St

tSU; STO

P

Fig. 9. I2C bus device recommended circuit

I2C bus

device

I2C bus

device

RS

RS RS

RS RP

RP

SDA0

(or SDA1)

SCL0

(or SCL1)

• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance can be used to reduce the spike noise caused

by CRT flashover.

– 17 –

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