ISL62383 データシートの表示（PDF） - Renesas Electronics
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ISL62383
Renesas Electronics
ISL62383 Datasheet PDF : 24 Pages
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ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be
sure that IP-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated RMS
current at FSW. Take into account that the rated value of a
capacitor can fade as much as 50% as the DC voltage across it
increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater than
the maximum input voltage, while a voltage rating of 1.5 times
is a preferred rating. Figure 28 is a graph of the input capacitor
RMS ripple current, normalized relative to output load current,
as a function of duty cycle and is adjusted for converter
efficiency. The normalized RMS ripple current calculation is
written as Equation 22:
ICINRMS,NORMALIZED= I--M-----A----X------------D------I--M----1-A---–-X----D--------+-----D--------1------2---k-------2----
(EQ. 22)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- k is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage
of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as:
D = -V----I-V-N---O----U-E----TF----F---
(EQ. 23)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side
MOSFET.
0.6
0.48
k=1
0.36
k = 0.75
k = 0.5
k = 0.25
0.24
k=0
0.12
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the upper
voltage tolerance of the input power source and the voltage
spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn off,
the high-side MOSFET turns off with a VDS of approximately
VIN - VOUT, plus the spike across it. The preferred low-side
MOSFET emphasizes low r DS(ON) when fully saturated to
minimize conduction loss. It should be noted that this is an
optimal configuration of MOSFET selection for low duty cycle
applications (D < 50%). For higher output, low input voltage
solutions, a more balanced MOSFET selection for high- and
low-side devices may be warranted.
For the low-side (LS) MOSFET, the power loss can be assumed
to be conductive only and is written as Equation 24:
PCON
_LS
ILO
A
2
D
rDSON_
LS
1
–
D
(EQ. 24)
For the high-side (HS) MOSFET, the its conduction loss is
written as Equation 25:
PCON_HS
=
IL
O
A
2
D
rD
S
O
N
_
H
S
D
(EQ. 25)
For the high-side MOSFET, the switching loss is written as
Equation 26:
PSW_HS = V-----I--N-------I--V----A----L---L---E--2--Y-------t--O-----N-------f--S----W--- + -V----I--N-------I--P----E----A----K--2-----t--O----F----F-------f-S----W----
(EQ. 26)
FN6665 Rev 6.00
October 23, 2015
Page 19 of 24
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