CS61575 データシートの表示（PDF） - Cirrus Logic

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CS61575

T1/E1 Line Interface

Cirrus Logic 

CS61574A CS61575

RTIP

1:2

RRING

Data

Level

Slicer

Edge

Detector

Data

Sampling

& Clock

Extraction

Clock

Phase

Selector

Jitter

Attenuator

RPOS

RNEG

RCLK

Continuously

Calibrated

Delay Line

Figure 10. Receiver Block Diagram

A block diagram of the receiver is shown in Fig-

ure 10. The two leads of the transformer (RTIP

and RRING) have opposite polarity allowing the

receiver to treat RTIP and RRING as unipolar sig-

nals. Comparators are used to detect pulses on

RTIP and RRING. The comparator thresholds are

dynamically established at a percent of the peak

level (50% of peak for E1, 65% of peak for T1;

with the slicing level selected by LEN2/1/0 in-

puts).

The leading edge of an incoming data pulse trig-

gers the clock phase selector. The phase selector

chooses one of the 13 available phases which the

delay line produces for each bit period. The out-

put from the phase selector feeds the clock and

data recovery circuits which generate the recov-

ered clock and sample the incoming signal at

appropriate intervals to recover the data.

Data sampling will continue at the periods se-

lected by the phase selector until an incoming

pulse deviates enough to cause a new phase to be

selected for data sampling. The phases of the de-

lay line are selected and updated to allow as much

as 0.4 UI of jitter from 10 kHz to 100 kHz, with-

out error. The jitter tolerance of the receiver

exceeds that shown in Figure 11. Additionally,

this method of clock and data recovery is tolerant

of long strings of consecutive zeros. The data

sampler will continuously sample data based on

its last input until a new pulse arrives to update

the clock phase selector.

The delay line is continuously calibrated using

the crystal oscillator reference clock. The delay

line produces 13 phases for each cycle of the ref-

erence clock. In effect, the 13 phases are

analogous to a 20 MHz clock when the reference

clock is 1.544 MHz. This implementation utilizes

the benefits of a 20 MHz clock for clock recovery

without actually having the clock present to im-

pede analog circuit performance.

300

138

100

28

10

PEAK-TO-PEAK

JITTER

(unit intervals)

1

.4

Minimum

Performance

AT&T 62411

.1

1

10

100 300 700 1k

10k

JITTER FREQUENCY

(Hz)

100k

Figure 11. Minimum Input Jitter Tolerance of Receiver

DS154F2

13

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