CXL1517N/1518N
Pin Description
Pin No. Symbol
1
VSS
2
VSS
3
IN-B
4
ABBL
5
VDD
6
IN-C
7
CLP
8
VDD
9
OUT-C
10
VGG
11 OUT-B
12 NC
13 NC
14 OUT-A
15 CDS
16
VSS
17
VSS
18 XDL2
19 XDL1
20
VDD
21 ABCN
22 ABOVF
23 IN-A
24 NC
I/O
Description
Comment
—
— GND
Analog
I Signal input B channel (Y)
O Autobias DC output for Y signal
Black level bias
— Power supply
Analog
I Signal input C channel (Y)
Black level bias
at no clamp > 100k
I Clamp pulse input
> 100k
— Power supply
Output circuit
O Signal output C channel
O Output circuit bias DC output
O Signal output B channel
—
—
—
—
O Signal output A channel
O DC output for CDS
— GND
Output circuit
— GND
Timing
I Clock pulse input 2
> 100k
I Clock pulse input 1
> 100k
— Power supply
Timing
O Autobias DC output for C signal
O Autobias DC output for overflow prevention circuit
I Signal input A channel (C)
Center level bias
at no clamp > 100k
—
—
–3–