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FAN8060 データシートの表示(PDF) - ON Semiconductor

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FAN8060 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin Configuration
EN 1
AVIN 2
PVIN 3
SW 4
PGND 5
10 AGND
9 FB
8 COMP
7 SS
6 SYNC
Figure 2. Pin Configuration (Top View)
Note:
1. Connect exposed PAD to AGND
Pin Definitions
Pin Name
Function
1
EN Enable. Enables operation when pulled to logic HIGH.
2
AVIN Analog Input Voltage. All internal control circuits are connected to this supply.
3
PVIN Power Input Voltage. Power stage supply voltage.
4
SW Switching Node. The drains of both PMOS and NMOS.
5
PGND Power Ground. Power return and source of the power NMOS
Synchronization. Use this pin to synchronize the part to an external clock. This pin also
6
SYNC
controls current limit threshold. Tie to ground for 1.0 A or tie to VIN for 0.5 A continuous load
current. When an external clock is applied, the default current setting is 1 A. This pin has a
pull-down resistor of 450 K.
7
SS Soft-Start. A capacitor connected between this pin and AGND can set soft-start time.
8
COMP
Compensation. Error amplifier output. Connect the external compensation network between
this pin and AGND.
9
FB Output Voltage Feedback. Connect through a resistor divider to set the output voltage.
10
AGND Analog Ground. Ground return for all internal control circuits.
© 2013 Fairchild Semiconductor Corporation
FAN8060 • Rev. 1.0.1
2
www.fairchildsemi.com

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