HI7190 データシートの表示（PDF） - Renesas Electronics
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HI7190 Datasheet PDF : 25 Pages
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HI7190
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
When reading the serial port, data is driven out of the HI7190
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Detailed Register Descriptions
Data Output Register
The Data Output Register contains 24 bits of converted data.
This register is a read only register.
BYTE 2
MSB 22
21
20
19
18
17
16
D23 D22 D21 D20 D19 D18 D17 D16
BYTE 1
15
14
13
12
11
10
9
8
D15 D14 D13 D12 D11 D10 D9
D8
BYTE 0
7
6
5
4
3
2
1 LSB
D7
D6
D5
D4
D3
D2
D1
D0
IR WRITE PHASE
CS
DATA TRANSFER PHASE - TWO-BYTE WRITE
SCLK
SDIO I0 I1 I2 I3 I4 I5 I6 I7
B0 B1 B2 B3 B4 B5 B6 B7
B8 B9 B10 B11 B12 B13 B14 B15
SDO
THREE-STATE
THREE-STATE
FIGURE 14. DATA WRITE CYCLE, SCLK IDLE LOW
IR WRITE PHASE
CS
DATA TRANSFER PHASE - TWO-BYTE WRITE
SCLK
SDIO
SDO
I0 I1 I2 I3 I4 I5 I6 I7
B0 B1 B2 B3 B4 B5 B6
B7
B15
B8 B9 B10 B11 B12 B13 B14
THREE-STATE
THREE-STATE
FIGURE 15. DATA WRITE CYCLE, SCLK IDLE HIGH
CS
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
SCLK
SDIO
SDO
I0 I1 I2 I3 I4 I5 I6 I7
B0 B1 B2 B3 B4 B5 B6 B7
B15
B8
B9 B10 B11 B12 B13 B14
FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW
FN3612 Rev 10.00
June 27, 2006
Page 19 of 25
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