CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

VP

The vertical display start position setting VP sets the value used to decode the internal counter. This internal

counter is reset at the ENB1 and 2 pulse fall position when VSYNC is input, and counts up at each ENB1 and

2 pulse fall position thereafter.

Therefore, when VSYNC is delayed relative to HSYNC and serial data HP is all L or a similar value, or when

the HP11 to 0 setting is large and the ENB pulses fall near the end of the horizontal period, the vertical display

start position is offset by 1H.

VSYNC

HSYNC

ENB1, 2

ENB1, 2

The counter is reset at this timing.

The counter is reset at this timing.

When the HP11 to 0 setting is large.

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