CXD3500R データシートの表示（PDF） - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

FRP1, 0

These bits are the data for switching the LCD AC conversion signal FRP pulse cycle. Normally set FRP1, 0 to

LL.

FRP0 can also be controlled externally. → See SLCNT.

1H

FRP1, 0: LL

(1F/1H inversion)

FRP1, 0: HL

(2F/1H inversion)

FRP1, 0: LH

(1F inversion)

FRP1, 0: HH

(2F inversion)

1F

FRPP3, 2, 1, 0

These bits adjust the FRP pulse transition point in 2-dot units.

The PRG pulse rise position is the same as the FRP pulse transition point, and is interlinked with FRPP3 to 0.

Tfrp

ENB1, 2

FRP

PCG

Tfrp setting range

PLSSL2, 1, 0

LLL

LLH

LHL

LHH

HLL

HLH

HHL

HHH

FRPP3, 2, 1, 0

LLLL

HHHH

16 clk

46 clk

24 clk

54 clk

36 clk

66 clk

52 clk

82 clk

68 clk

98 clk

58 clk

88 clk

62 clk

92 clk

72 clk

102 clk

– 21 –

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