CXD1961AQ データシートの表示（PDF） - Sony Semiconductor

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CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

Description of CPU Interface Registers

Sub address 00 (hex)

Read

INP_LEV Input level estimation

INP7 to INP0

(MSB) (LSB)

Upper 8 bit of I2 + Q2 of analog I/Q input.

(Ex.) The value is about 40 (hex) when the analog I/Q amplitude is half the input

range.

Sub address 01 (hex)

PWM7 to PWM0

(MSB) (LSB)

Read

PWM_VAL AGC PWM output value

PWM output value of AGC control.

Sub address 02 (hex)

AFC7 to AFC0

(MSB) (LSB)

AFC7: Sign

Read

AFC_VAL Carrier offset value

Carrier offset estimation

Carrier offset = (Symbol rate) × AFC [7:0] ÷ 512 (Hz)

Ex.) 20MSPS AFC [7:0] = 11110000 (bin)

offset = 20MHz × (–16) ÷ 512

= –625kHz

In this case, by changing tuner PLL value by -625kHz, the offset may be

cancelled.

Sub address 03 (hex)

Sub address 04 (hex)

Read

Read

QBEC_LOW Bit error count at QPSK output

QBEC_UPR Bit error count at QPSK output

QBEC15 to QBEC0

(MSB) (LSB)

Bit error count at the QPSK output (16 bit).

Measuring period is set by TQBEC [1:0] of CPU I/F register 11 (hex) .

BER is the ratio of QBEC [15:0] and the measuring period.

QBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.

Sub address 05 (hex)

Sub address 06 (hex)

Read

Read

VBEC_LOW Bit error count at Viterbi output

VBEC_UPR Bit error count at Viterbi output

VBEC15 to VBEC0

(MSB) (LSB)

Bit error count at the Viterbi output (16 bit).

Measuring period is 204 × 8 × 1280 = 2,088,960.

BER is the ratio of VBEC [15:0] and 2,088,960.

VBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.

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