CXD3511 データシートの表示（PDF） - Sony Semiconductor
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CXD3511 Datasheet PDF : 79 Pages
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CXD3511Q
Parallel I/F Block AC Characteristics (Topr = –20 to +75°C, VDD1 = 2.5 ± 0.2V, VDD2 = 3.3 ± 0.3V, VSS = 0V)
Item
PCTL setup time with respect to rise of PCLK
PCTL hold time with respect to rise of PCLK
PDAT[9:0] setup time with respect to rise of PCLK
PDAT[9:0] hold time with respect to rise of PCLK
PCLK pulse width
Symbol Min. Typ. Max.
tcs
8T∗5
—
—
tch
8T
—
—
tds
4T
—
—
tdh
4T
—
—
tw
4T
—
—
∗5 T: Master clock (CLKP, CLKN, CLKC) period [ns]
Timing Definition
PCTL
PCLK
PDAT[9:0]
tcs
50%
tw
50%
tds
50%
tch
tw
50%
tdh
50%
50%
VDD2
VSS
VDD2
VSS
VDD2
VSS
Power-on and Initialization of Internal Circuit
As for this IC, two systems of supply voltage should be turned on simultaneously. The initialization of the
internal circuit should be also performed by maintaining the system clear pin at low during the specified time
after setting the supply voltage in the range of recommended operating conditions and stabilizing as shown in
the figure below. Keep in mind that the internal circuit may not be initialized correctly if system clear
cancellation is performed before the supply voltage is set in the range of the recommended operating
conditions.
VDD1, VDD2
XCLR1, XCLR2,
XCLR3
TR
TR > 200ns
VDD1, VDD2
VSS
VDD2
VSS
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