CXD3511 データシートの表示（PDF） - Sony Semiconductor

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CXD3511

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3511Q

2. RGB Signal and OSD Signal Pipeline Delay

The RGB signal I/O pipeline delay is 54 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 34

dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the

figures below. This relationship is the same for the OSD, YM and YS signals.

(1) CLKPOL = L

HDIN input (negative polarity)

Dot clock

1/2 frequency-divided clock

R1, G1, B1IN

R2, G2, B2IN

CLKOUT

R1, G1, B1OUT

R2, G2, B2OUT

N – 2 N N + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18

N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19

N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36

N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35

(2) CLKPOL = H

HDIN input (negative polarity)

Dot clock

1/2 frequency-divided clock

R1, G1, B1IN

N – 2 N N + 2 N + 4 N + 6 N + 8 N + 10 N + 12 N + 14 N + 16 N + 18

R2, G2, B2IN

N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19

CLKOUT

R1, G1, B1OUT N – 56 N – 54 N – 52 N – 50 N – 48 N – 46 N – 44 N – 42 N – 40 N – 38 N – 36

R2, G2, B2OUT N – 55 N – 53 N – 51 N – 49 N – 47 N – 45 N – 43 N – 41 N – 39 N – 37 N – 35

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