CXD3511 データシートの表示（PDF） - Sony Semiconductor

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CXD3511

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3511Q

(j) Pattern generator block

This block generates and outputs the set fixed pattern independently of the input signal. This function is valid

when PG_ON = 1. When PG_R (G, B)_ON is "0", the signal level goes to 000h respectively for R, G and B.

The raster display pattern is displayed in the effective area, and all other display patterns are displayed in the

window area. Here, the effective area is set by PG_HST, PG_HSTP, PG_VST and PG_VSTP, and the window

area is set by PG_HWST, PG_HWSTP, PG_VWST and PG_VWSTP.

The display pattern signal level is set independently for R, G and B by PG_SIG1R (G, B)[9:0] and PG_SIG2R

(G, B)[9:0]. Within the effective area, the pattern and non-pattern signal levels can be switched by PG_R (G,

B)_SEL. At this time, the signal level outside the effective area goes to 000h. During horizontal ramp, horizontal

stair, vertical ramp and vertical stair display, the PG_SIG1R (G, B)[9:0] and PG_SIG2R (G, B)[9:0] settings are

invalid.

The display patterns and signal levels are as follows.

(1) Raster display

When PG_PAT[2:0] = 0h, a raster is displayed.

PG_SIG2R (G, B)

PG_R (G, B)_SEL

0

PG_PAT[2:0]

0h

PG_STRP_SW

x

PG_STAIR_SW

x

PG_SIG1R (G, B)

PG_R (G, B)_SEL

1

PG_PAT[2:0]

0h

PG_STRP_SW

x

PG_STAIR_SW

x

– 21 –

x: Don't care

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