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1048EA データシートの表示（PDF） - Lattice Semiconductor

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1048EA

In-System Programmable High Density PLD

Lattice Semiconductor

1048EA Datasheet PDF : 14 Pages

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Specifications ispLSI 1048EA

Functional Block Diagram

Figure 1. ispLSI 1048EA Functional Block Diagram

RESET

GOE 0

GOE 1

VCCIO

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80

IN IN

11 10

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8

Generic

Logic Blocks

(GLBs)

Input Bus

Output Routing Pool (ORP)

F7 F6 F5 F4 F3 F2 F1 F0

Input Bus

Output Routing Pool (ORP)

E7 E6 E5 E4 E3 E2 E1 E0

Global

Routing

Pool

(GRP)

IN 7

IN 6

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

Megablock

TDI

TDO

TMS

TCK

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool (ORP)

Input Bus

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool (ORP)

Input Bus

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

IN 2

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

YYYY

0123

0139F/1048EA

The device also has 96 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered

input, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source

2mA or sink 8mA. Each output can be programmed

independently for fast or slow output slew rate to

minimize overall output switching noise. By connecting

the VCCIO pin to a common 5V or 3.3V power supply,

I/O output levels can be matched to 5V or 3.3V compat-

ible voltages.

Eight GLBs, 16 I/O cells, dedicated inputs (if available)

and one ORP are connected together to make a

Megablock (Figure 1). The outputs of the eight GLBs are

connected to a set of 16 universal I/O cells by the ORP.

Each ispLSI 1048EA device contains six Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1048EA device are selected using

the Clock Distribution Network. Four dedicated clock pins

(Y0, Y1, Y2 and Y3) are brought into the distribution

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

also be driven from a special clock GLB (D0). The logic

of this GLB allows the user to create an internal clock

from a combination of internal signals within the device.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 1048EA are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the ispDesignEXPERT software tools.

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