Test Diagrams
VON
An
Bn
VSW
GND
ION
/O
E
GND
RO = O / ION
V Sel= 0 rVcc
o
FNiguVreN3. On Resistance
An
VSW
GND RS
Bn
CL
RL VOUT
GND
VSel
GND
RL , RS, and CL are functions of the application
environment (see AC tables for specific values).
CL includes test fixture and stray capacitance.
Figure 4. AC Test Circuit Load
tRISE= 2.5ns
tFALL = 2.5ns
VCC
Input – V/OE , VSel
10%
GND
VOH
Output- VOUT
VOL
90%
VCC /2
90%
VCC /2
90%
tON
tOFF
10%
90%
Figure 5. Turn-On / Turn-Off Waveform s
tRISE= 500ps
tFALL = 500ps
+400mV
- 400mV
10%
90%
0V
90%
10%
Output
Figure 6. Propagation Delay
(try to – 500ps)
Capacitance
Meter
An
Bn
/OE
VSel = 0 or Vcc
Figure 8. Channel Off Capacitance
tPHL
tPLH
Figure 7. Intra-Pair Skew Test tSK(P)
Capacitance An
Meter
Bn
/OE
V Sel = 0 or Vcc
Figure 9. Channel On Capacitance
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