INTEL82801E データシートの表示（PDF） - Intel

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INTEL82801E

Intel® 82801E Communications I/O Controller Hub (C-ICH)

Intel 

Intel® 82801E C-ICH

Table 6. 82801E C-ICH Signal Description (Sheet 7 of 11)

Signal

Type

Description

PIRQ[E:F]#

PIRQ[G]#/GPIO[4]

PIRQ[H]#/GPIO[5]

PLOCK#

PWROK

RCIN#

REQ[3:0]#

REQ[5]#

/REQ[B]#

/GPIO[1]

REQ[A]#

/GPIO[0]

REQ[B]#

/REQ[5]#

/GPIO[1]

RESERVED1

RESERVED2

RI#

RSM_PWROK

RSMRST#

RTCRST#

RTCX1

RTCX2

I/OD

I/O

I

I

I

I

—

I

I

I

I

Special

Special

PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be

routed to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering

section. Each PIRQx# line has a separate Route Control Register.

In APIC mode, these signals are connected to the internal I/O APIC in the

following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21,

PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. If not needed for interrupts,

these signals can be used as GPIO.

PCI Lock: PLOCK# indicates an exclusive bus operation and may require

multiple transactions to complete. 82801E C-ICH asserts PLOCK# when it

performs non-exclusive transactions on the PCI bus.

Power OK: When asserted, PWROK is an indication to the 82801E C-ICH

that core power and PCICLK have been stable for at least 1 ms. PWROK can

be driven asynchronously. When PWROK is negated, the 82801E C-ICH

asserts PCIRST#.

Keyboard Controller Reset Processor: The keyboard controller can

generate INIT# to the processor. This saves the external OR gate with the

82801E C-ICH’s other sources of INIT#. When the 82801E C-ICH detects the

assertion of this signal, INIT# is generated for 16 PCI clocks.

PCI Requests: The 82801E C-ICH supports up to four masters on the PCI

bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other,

but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be

used as GPIO[1].

NOTE: REQ[0]# is programmable to have improved arbitration latency for

supporting PCI-based 1394 controllers.

PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests

for the purpose of running ISA-compatible DMA cycles over the PCI bus. This

is used by devices such as PCI-based Super I/O or audio codecs that need to

perform legacy 8237 DMA but have no ISA bus.

When not used for PC/PCI requests, these signals can be used as General

Purpose Inputs. Instead, REQ[B]# can be used as the fourth PCI bus request.

This signal must have an external pull up to Vcc3_3.

Ring Indicate: From the modem interface. This signal can be enabled as a

wake event; this is preserved across power failures.

Resume Well Power OK: When asserted, this signal is an indication to the

82801E C-ICH that the resume well power has been stable for at least 10 ms.

NOTE: The 82801E C-ICH does not use the Resume Well Power OK signal.

Resume Well Reset: RSMRST# is used for resetting the resume power

plane logic.

NOTE: The 82801E C-ICH does not use the Resume Well Reset signal.

RTC Reset: When asserted, this signal resets register bits in the RTC well

and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This

signal is also used to enter the test modes documented in “Test Signals” on

page 49.

NOTE: Clearing CMOS in an 82801E C-ICH-based platform can be done by

using a jumper on RTCRST# or GPI, or using SAFEMODE strap.

Implementations should not attempt to clear CMOS by using a

jumper to pull VccRTC low.

Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no

external crystal is used, then RTCX1 can be driven with the desired clock

rate.

Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no

external crystal is used, then RTCX2 should be left floating.

Advance Information Datasheet

31

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