LD3985M33R(2017) データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

LD3985M33R
(Rev.:2017)

Ultra low drop and low noise BiCMOS voltage regulators

STMicroelectronics 

Pin configuration

2

Pin configuration

Figure 2. Pin connection (top view)

LD3985

Table 1. Pin description

Pin

Symbol

Name and function

1

VI

Input voltage of the LDO

2

GND Common ground

3

VINH

Inhibit input voltage: ON mode when VINH ≥ 1.2 V, OFF mode when VINH

≤ 0.4 V (Do not leave it floating, not internally pulled down/up)

4

BYPASS

Bypass pin: an external capacitor (usually 10 nF) has to be connected to

minimize noise voltage

5

VO

Output voltage of the LDO

4/18

DocID9587 Rev 16

Share Link: