CY7C1399D データシートの表示（PDF） - Cypress Semiconductor
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CY7C1399D Datasheet PDF : 10 Pages
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PRELIMINARY
CY7C1399D
Capacitance[5]
Parameter
CIN: Addresses
CIN: Controls
COUT
Description
Input Capacitance
Output Capacitance
Thermal Resistance[5]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)[5]
Thermal Resistance
(Junction to Case)[5]
AC Test Loads and Waveforms
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
5
pF
6
pF
6
pF
Test Conditions
All – Packages
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
TBD
TBD
Unit
°C/W
°C/W
10-ns Device
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5V
(a)
30 pF*
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
12-ns Device
3.3V
OUTPUT
R1 317Ω
30pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
(b)
High-Z characteristics:
3.0V
10%
GND
≤ 3 ns
ALL INPUT PULSES
90%
90%
10%
≤ 3 ns
(d)
3.3V
R1 317 Ω
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(c)
R2
351Ω
Switching Characteristics Over the Operating Range [7]
1399D-10
1399D-12
1399D-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
100
100
µs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change 3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
tLZOE
tHZOE
tLZCE
OE LOW to Data Valid
OE LOW to Low Z[8]
OE HIGH to High Z[8, 9]
CE LOW to Low Z[8]
5
5
6
ns
0
0
0
ns
5
5
6
ns
3
3
3
ns
Notes:
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
Document #: 38-05467 Rev. *C
Page 4 of 10
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