OX16PCI952 データシートの表示（PDF） - Oxford Semiconductor

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OX16PCI952

Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface

Oxford Semiconductor 

OXFORD SEMICONDUCTOR LTD.

OX16PCI952

Pins

Serial port pins (Contd)

91

Dir1

Name

XI XTLI

90

XO XTLO

Description

Crystal oscillator input or external clock pin, for the UART

channels. Crystal oscillator frequency maximum 40MHz.

Maximum frequency 60MHz, via external clock source.

Crystal oscillator output

Pins

Parallel port

87

87

86

85

85

81

81

84

83

80

80

79

79

78

78

68, 69, 70, 71,

72, 73, 74, 75

66

Dir1

Name

Description

I ACK#

Acknowledge Signal in SPP mode. ACK# is asserted (low)

by the peripheral to indicate that a successful data transfer

has taken place.

I INTR#

I PE

I BUSY

INTR# pin in EPP mode. Function identical to ACK#.

Paper Empty.

Activated by printer when it runs out of paper.

Busy Signal in SPP mode. BUSY is asserted (high) by the

peripheral when it is not ready to accept data

I WAIT#

OD 2 SLIN#

Wait signal in EPP mode.

Handshake signal for interlocked IEEE 1284 compliant EPP

cycles.

Select signal in SPP mode. Asserted by host to select the

peripheral.

O ADDRSTB#

I SLCT

I ERR#

OD 2 INIT#

Address strobe in EPP mode. Provides address read and

write strobe.

Peripheral selected.

Asserted by peripheral when selected.

Error.

Held low by the peripheral during an error condition.

Initialize signal in SPP mode. Commands the peripheral to

initialize.

O INIT#

OD 2 AFD#

Initialize signal in EPP mode. Function identical to SPP.

Auto Feed signal in SPP mode.

O DATASTB#

OD 2 STB#

Data strobe signal in EPP mode. Provides data read and

write strobe.

Strobe signal in SPP mode. Used by the peripheral to latch

data currently available on the PD[7:0] lines.

O WRITE#

I/O 2 PD[7:0]

Write signal in EPP mode. Indicates a write cycle when low

and a read cycle when high.

Parallel port bi-directional data bus

O LOCAL_TRANS_EN Parallel Port Data Output Enable.

This pin can be used by external transceivers. It is high when

PD[7:0] are in output mode, and low when they are in input

mode.

DS-0028 Jul 05

External-Free Release

Page 11

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