MAX1450 データシートの表示（PDF） - Maxim Integrated
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MAX1450 Datasheet PDF : 12 Pages
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MAX1450
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
Pin Description
PIN
1
2, 3,
12, 16
NAME
INP
I.C.
FUNCTION
Positive Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
Internally connected. Leave unconnected.
Offset TC Sign Bit Input. A logic low inverts VOFFTC with respect to VSS. This pin is internally pulled
4
SOTC to VSS via a 1MΩ (typical) resistor. Connect to VDD to add VOFFTC to the PGA output, or leave
unconnected (or connect to VSS) to subtract VOFFTC from the PGA output.
Offset Sign Bit Input. A logic low inverts VOFFSET with respect to VSS. This pin is internally pulled to VSS
5
SOFF via a 1MΩ (typical) resistor. Connect to VDD to add VOFFSET to the PGA output, or leave unconnected
(or connect to VSS) to subtract VOFFSET from the PGA output.
6
A1
PGA Gain-Set Input. Internally pulled to VSS via a 1MΩ (typical) resistor. Connect to VDD for a logic high
or VSS for a logic low.
7
A0
PGA Gain-Set LSB Input. Internally pulled to VSS via a 1MΩ (typical) resistor. Connect to VDD for a logic
high or VSS for a logic low.
8
OFFTC
Offset TC Adjust. Analog input summed with PGA output and VOFFSET. Input impedance is typically
1MΩ. Rail-to-rail input range.
9
OFFSET
Offset Adjust Input. Analog input summed with PGA output and VOFFTC. Input impedance is typically
1MΩ. Rail-to-rail input range.
10
BBUF
Buffered Bridge-Voltage Output (the voltage at BDRIVE). Use with correction resistor RSTC to correct for
FSO tempco.
11
FSOTRIM Bridge Drive Current-Set Input. The voltage on this pin sets the nominal IISRC. See the Bridge Drive section.
13
A2
PGA Gain-Set MSB Input. Internally pulled to VSS via a 11kΩ (typical) resistor. Connect to VDD for a
logic high or VSS for a logic low.
14
OUT
PGA Output Voltage. Connect a 0.1μF capacitor from OUT to VSS.
15
VDD
Positive Supply Voltage Input. Connect a 0.1μF capacitor from VDD to VSS.
17
ISRC Current-Source Reference. Connect a 50kΩ (typical) resistor from ISRC to VSS.
18
BDRIVE Sensor Excitation Current Output. This pin drives a nominal 0.5mA through the bridge.
19
VSS
Negative Power-Supply Input.
20
INM
Negative Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
Detailed Description
Analog Signal Path
The MAX1450’s signal path is fully differential and com-
bines the following three stages: a 3-bit PGA with select-
able gains of 39, 65, 91, 117, 143, 169, 195, and 221; a
summing junction; and a differential to singleended output
buffer (Figure 1).
Programmable-Gain Amplifier
The analog signal is first fed into a programmable-gain
instrumentation amplifier with a CMRR of 90dB and a
common-mode input range from VSS to VDD. Pins A0, A1,
and A2 set the PGA gain anywhere from 39V/V to 221V/V
(in steps of 26).
A2 A1 A0
INP
PGA
INM
OFFTC SOTC
±
∑
A = 1 OUT
±
OFFSET SOFF
Figure 1. Signal-Path Functional Diagram
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