CGY184 データシートの表示（PDF） - Infineon Technologies
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CGY184 Datasheet PDF : 14 Pages
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CGY184 application board:
CGY 184
1n
33p
15p
3k9
1n
1n
1n
2. 2n H
33p
120 p
1n
4,7µ
Layout size is 32mm x 19mm
Connections:
l Vd
2.7 to 6VDC, pulsed (PCN: 12,5% duty cycle, ton=0.577ms)
l Vaux 2.7 to 6VDC
l Vcontrol 0.2 to 2.2VDC (0.2V: min Pout, 2.2V: max Pout)
l CLK 5 MHz to 15 MHz (with a 10uH inductor)
or 150 kHz to 250 kHz (with a 100uH inductor instaed of the 10uH)
(rectangular signal, 50% duty, 0 Volt to Vd voltage level)
Power on sequence:
1. continuous clock (CLK) on
2. turn on Vaux ==> check negative voltage at pin#16 (-4......-10V)
3. turn on Vcon (may be at the same time as 2)
turn on Drainvoltage Vd
turn on Input Power
Operation without using the negative voltage generator:
If you don’t want to use the internal negative voltage generator, you can also apply -4....-6 V
at pin#15 (Vneg-Pin). In this case the passive devices at the pins 1, 14 and 16 are not
necessary (1 inductor and 3 capacitors).
Siemens Aktiengesellschaft
12
Semiconductor Group
12
23.07.97
HL HF19P9E8-G11a-A0s1
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