CS51033GDR8(2002) データシートの表示（PDF） - ON Semiconductor

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CS51033GDR8
(Rev.:2002)

Fast PFET Buck Controller

ON Semiconductor 

CS51033

Buck Regulator Operation

A block diagram of a typical buck regulator is shown in

Figure 4. If we assume that the output transistor is initially

off, and the system is in discontinuous operation, the

inductor current IL is zero and the output voltage is at its

nominal value. The current drawn by the load is supplied by

the output capacitor CO. When the voltage across CO drops

below the threshold established by the feedback resistors R1

and R2 and the reference voltage VREF, the power transistor

Q1 switches on and current flows through the inductor to the

output. The inductor current rises at a rate determined by

(VIN – VOUT)/Load. The duty cycle (or “on” time) for the

CS51033 is limited to 80%. If output voltage remains higher

than nominal during the entire COSC change time, the Q1

does not turn on, skipping the pulse.

Q1

VIN

CIN

Control

L

D1

Feedback

R1

CO

R2

RLOAD

Figure 4. Buck Regulator Block Diagram.

Charge Pump Circuit

(Refer to the CS51033 Application Diagram on page 2).

An external charge pump circuit is necessary when the VC

input voltage is below 5.0 V to ensure that there is suffifient

gate drive voltage for the external FET. When VIN is applied,

capacitors C1 and C2 will be charged to a diodes drop below

VIN via diodes D2 and D4, respectively. When the PFET

turns on, it’s drain voltage will be approximately equal to

VIN. Since the voltage across C1 can not change

instantaneously, D2 is reverse biased and the anode voltage

rises to approximately 2.0 × 3.3 V – VD2. C1 transfers some

of its stored charge C2 via D3. After several cycles there is

sufficient gate drive voltage.

APPLICATIONS INFORMATION

DESIGNING A POWER SUPPLY WITH THE CS51033

Specifications

• VIN = 3.3 V ±10% (i.e. 3.63 V max., 2.97 V min.)

• VOUT = 1.5 V ±2.0%

• IOUT = 0.3 A to 3.0 A

• Output ripple voltage < 33 mV.

• FSW = 200 kHz

1) Duty Cycle Estimates

Since the maximum duty cycle D, of the CS51033 is

limited to 80% min., it is best to estimate the duty cycle for

the various input conditions to see that the design will work

over the complete operating range.

The duty cycle for a buck regulator operating in a

continuous conduction mode is given by:

D

+

VOUT

VIN *

) VD

VSAT

In this case we can assume that VD = 0.6 V and VSAT =

0.6 V so the equation reduces to:

D

+

VOUT

VIN

From this, the maximum duty cycle DMAX is 53%, this

occurs when VIN is at it’s minimum while the minimum duty

cycle DMIN is 0.35%.

2) Switching Frequency and On and Off Time

Calculations

FSW = 200 kHz. The switching frequency is determined

by COSC, whose value is determined by:

COSC +

FSW

ǒ Ǔ 95

^ 470 pF

ǒ Ǔ ǒ Ǔ 1 *

FSW

3 106

*

30 103 2

FSW

T

+

1.0

FSW

+

5.0

ms

where:

VSAT = RDS(ON) × IOUT Max.

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