ZL30415 データシートの表示（PDF） - Zarlink Semiconductor Inc

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ZL30415

SONET/SDH Clock Multiplier PLL

Zarlink Semiconductor Inc 

ZL30415

Data Sheet

4.2.2 Interfacing to OC-CLKo Output

4.2.2.1 LVPECL to LVPECL Interface

The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and

19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω

termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The

terminating resistors should be placed close to the LVPECL receiver.

+3.3 V

Typical resistor values: R1 = 127Ω, R2 =82.5Ω

ZL30415

VCC

0.1uF

LVPECL

Driver

OC-CLKoP

OC-CLKoN

GND

Z=50Ω

Z=50Ω

VCC=+3.3 V

R1

R1

LVPECL

Receiver

R2

R2

Figure 9 - LVPECL to LVPECL Interface

11

Zarlink Semiconductor Inc.

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