5962-0420501HPA データシートの表示（PDF） - Broadcom Corporation
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5962-0420501HPA Datasheet PDF : 18 Pages
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HCPL-5150 and HCPL-5151,
DLA SMD 5962-04205
Data Sheet
Applications Information
Eliminating Negative IGBT Gate Drive
To keep the IGBT firmly off, the HCPL-515x has a very low
maximum VOL specification of 1.0V. The HCPL-515x realizes this
very low VOL by using a DMOS transistor with 4Ω (typical) on
resistance in its pull down circuit. When the HCPL-515x is in the
low state, the IGBT gate is shorted to the emitter by Rg + 4Ω.
Minimizing Rg and the lead inductance from the HCPL-515x to
the IGBT gate and emitter (possibly by mounting the
HCPL-515x on a small PC board directly above the IGBT) can
eliminate the need for negative IGBT gate drive in many
applications as shown in Figure 25. Care should be taken with
such a PC board design to avoid routing the IGBT collector or
emitter traces close to the HCPL-515x input, as this can result in
unwanted coupling of transient signals into the HCPL-515x and
degrade performance. (If the IGBT drain must be routed near
the HCPL-515x input, then the LED should be reverse-biased
when in the off state, to prevent the transient signals coupled
from the IGBT drain from turning on the HCPL-515x.)
Selecting the Gate Resistor (Rg) to Minimize IGBT
Switching Losses
Step 1: Calculate Rg Minimum from the IOL Peak
Specification.
The IGBT and Rg in Figure 26 can be analyzed as a simple RC
circuit with a voltage supplied by the HCPL-515x.
Rg =
(V CC – VEE – V OL )
I OLPEAK
= (V CC – V EE – 1.7V)
I OLPEAK
= (1 5V + 5V – 1.7V)
0.6A
= 30.5:
The VOL value of 2V in the previous equation is a conservative
value of VOL at the peak current of 0.6A (see Figure 6). At lower
Rg values, the voltage supplied by the HCPL-515x is not an ideal
voltage step. This results in lower peak currents (more margin)
than predicted by this analysis. When negative gate drive is not
used, VEE in the previous equation is equal to zero volts.
Step 2: Check the HCPL-515x Power Dissipation and
Increase Rg if Necessary.
The HCPL-515x total power dissipation (PT) is equal to the sum
of the emitter power (PE) and the output power.
PT = P E + PO
PE = I Fu VF u Duty Cycle
PO = PO(BIAS) + PO (SWITCHING)
= I CC u (V CC – VEE )
+ E SW (Rg, Qg) u f
(PO):
For the circuit in Figure 26 with IF (worst case) = 18 mA:
PE = 18 mA u 1.8V u 0.8 = 26 mW
PO = 4.25 mA u 20V + 2.0PJ u 20 kHz
= 85 mW + 40 mW
= 125 mW
> 112 mW (PO(MAX) at 125oC =
250 mW – 23oC u 6 mW/oC)
Rg = 30.5Ω, Max Duty Cycle = 80%, Qg = 250 nC, f = 20 kHz and
TA max = 125°C:
The value of 4.25 mA for ICC in the previous equation was
obtained by derating the ICC max of 5 mA (which occurs at
–55°C) to ICC max at 125°C.
P O(SWITCHING MAX)
= PO(MAX) – PO(BIAS)
= 112 mW – 85 mW
= 27 mW
E SW(MAX) = PO(SWITCHING MAX)
f
= 27 mW
20 kHz
= 1.35 PJ
Since PO for this case is greater than PO(MAX), Rg must be
increased to reduce the HCPL-515x power dissipation.
For Qg = 250 nC, from Figure 27, a value of ESW = 1.35 μJ gives a
Rg = 90Ω.
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