X28HC64 データシートの表示（PDF） - Renesas Electronics
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X28HC64 Datasheet PDF : 18 Pages
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X28HC64
Write Cycle Limits
PARAMETER
SYMBOL
MIN
(Note 10)
TYP
(Note 11)
MAX
(Note 10)
UNIT
Write Cycle Time (Note 15)
tWC
2
5
ms
Address Set-Up Time
tAS
0
ns
Address Hold Time
tAH
50
ns
Write Set-Up Time
tCS
0
ns
Write Hold Time
tCH
0
ns
CE Pulse Width
tCW
50
ns
OE High Set-Up Time
tOES
0
ns
OE High Hold Time
tOEH
0
ns
WE Pulse Width
tWP
50
ns
WE HIGH Recovery (Note 16)
tWPH
50
ns
Data Valid (Note 16)
tDV
1
µs
Data Setup
tDS
50
ns
Data Hold
tDH
0
ns
Delay to Next Write (Note 16)
tDW
10
µs
Byte Load Cycle
tBLC
0.15
100
µs
NOTES:
15. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
16. tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
ADDRESS
CE
tAS
tAH
tCS
tWC
tCH
OE
WE
DATA IN
DATA OUT
tOES
tOEH
tWP
tDV
DATA VALID
tDS
tDH
HIGH Z
FIGURE 15. WE CONTROLLED WRITE CYCLE
FN8109 Rev 4.00
June 27, 2016
Page 12 of 18
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