2760A25 データシートの表示（PDF） - Maxim Integrated

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2760A25

High-Precision Li+ Battery Monitor

Maxim Integrated 

DS2760

POWER MODES

The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually

measures current, voltage and temperature to provide data to the host system and to support current

accumulation and Li+ safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The

DS2760 enters Sleep Mode when any of the following conditions occurs:

§ the PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than

2 seconds (pack disconnection)

§ the voltage on VIN drops below undervoltage threshold VUV for tUVD (cell depletion)

§ the pack is disabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 returns to Active Mode when any of the following occurs:

§ the PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high

(pack connection)

§ the PS pin is pulled low (power switch)

§ the voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit

set to 0

§ the pack is enabled through the issuance of a SWAP command (SWEN bit =1)

The DS2760 defaults to Sleep Mode when power is first applied.

LI+ PROTECTION CIRCUITRY

During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from

overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents

(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and

summarized in Table 2 and Figure 3.

LI+ PROTECTION CONDITIONS AND DS2760 RESPONSES Table 2

Condition

Activation

Release

Name

Threshold Delay

Response

Threshold

Overvoltage

Undervoltage

Overcurrent, Charge

Overcurrent, Discharge

Short Circuit

VIN > VOV

VIN < VUV

VIS > VOC(2)

VIS < -VOC(2)

VSNS > VSC

tOVD

tUVD

tOCD

tOCD

tSCD

CC high

CC , DC high,

Sleep Mode

CC , DC high

DC high

DC high

VIN < VCE

VPLS > VDD(1)

(charger connected)

VPLS < VDD – VTP(3)

VPLS > VDD – VTP(4)

VPLS > VDD – VTP(4)

VIS = VIS1 – VIS2. Logic high = VPLS for CC and VDD for DC . All voltages are with respect to VSS. ISNS

references current delivered from pin SNS.

(1) If VDD <2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD

charges the battery and allows VDD to exceed 2.2V.

(2) for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of

current: ISNS > IOC for charge direction and ISNS < -IOC for discharge direction

(3) with test current ITST current flowing from PLS to VSS (pull-down on PLS)

(4) with test current ITST current flowing from VDD to PLS (pull-up on PLS)

Overvoltage. If the voltage of the cell exceeds overvoltage threshold VOV for a period longer than

overvoltage delay tOVD, the DS2760 shuts off the external charge FET and sets the OV flag in the

Protection Register. When the cell voltage falls below charge enable threshold VCE, the DS2760 turns the

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