ISL85402 データシートの表示（PDF） - Renesas Electronics

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ISL85402

2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

Renesas Electronics 

ISL85402

C3

=

R-----o---C----o----–----3----R----c---C----o-

3R1

R3 = -R--3--o--R--–--c--3-R---R-1---c-

Case B: ESR zero

---------1-----------

2RcCo

larger than (0.35 to 0.5)fs

(EQ. 27)

(EQ. 28)

C3

=

0----.-3----3----R----o---C----o---f--s----–-----0---.--4---6--

fs

R

1

R3 = -0---.-7----3----R----oR---C-1---o---f--s----–-----1--

(EQ. 29)

(EQ. 30)

2. Derive R2 and C1.

The loop gain Lv(S) at cross over frequency of fc has unity gain.

Therefore, C1 is determined by Equation 31.

C1

=

---R----1-----+-----R----3------C---3--

2

fc

Rt

R1

C

o

(EQ. 31)

The compensator zero CZ1 can boost the phase margin and

bandwidth. To put CZ1 at 2 times of cross cover frequency fc is a

good start point. It can be adjusted according to specific design.

R1 can be derived from Equation 32.

R2

=

---------1---------

4fcC1

(EQ. 32)

Example: Vin = 12V, Vo = 5V, Io = 2A, fs = 500kHz,

Co = 60µF/3m, L = 10µH, Rt = 0.20V/A, fc = 50kHz, R1=105k,

RBIAS = 20k.

Select the crossover frequency to be 35kHz. Since the output

capacitors are all ceramic, use Equation 29 and 30 to derive R3

to be 20k and C3 to be 470pF.

Then use Equation 31 and 32 to calculate C1 to be 180pF and

R2 to be 12.7k. Select 150pF for C1 and 15k for R2.

There is approximately 30pF parasitic capacitance between

COMP to FB pins that contributes to a high frequency pole.

Figure 31 shows the simulated bode plot of the loop. It is shown

that it has 26kHz loop bandwidth with 70° phase margin and -28

dB gain margin.

Note in applications where the PFM mode is desired especially

when type III compensation network is used, the value of the

capacitor between the COMP pin and the FB pin (not the

capacitor in series with the resistor between COMP and FB)

should be minimal to reduce the noise coupling for proper PFM

operation. No external capacitor between COMP and FB is

recommended at PFM applications.

80

60

40

20

0

-20

-40

-60

100

Loop Gain

1,000

10,000

100,000

Frequency

1,000,000

Phase Margin

180

160

140

120

100

80

60

40

20

0

100

1,000

10,000

100,000

Frequency

FIGURE 31. SIMULATED LOOP BODE PLOT

1,000,000

Boost Inductor

Besides the need to sustain the current ripple to be within a

certain range (30% to 50%), the boost inductor current at its

soft-start is a more important perspective to be considered in

selection of the boost inductor. Each time the boost starts up,

there is a fixed 500µs soft-start time when the duty cycle

increases linearly from tMIN(ON)*Fs to ~50%. Before and after

boost start-up, the boost output voltage will jump from

VIN_BOOST to voltage (VIN_BOOST + VOUT_BUCK). The design target

in boost soft-start is to ensure the boost input current is

sustained to minimum but capable to charge the boost output

voltage to have a voltage step equaling to VOUT_BUCK. A big

inductor will block the inductor current to increase and not high

enough to be able to charge the output capacitor to the final

steady state value (VIN_BOOST + VOUT_BUCK) within 500µs. A

6.8µH inductor is a good starting point for its selection in design.

The boost inductor current at start-up must be checked by

oscilloscope to ensure it is under acceptable range. It is

suggested to run the iSim model, which is available on the

internet to assist in designing the proper inductor value.

FN7640 Rev 1.00

April 25, 2013

Page 19 of 22

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